1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method and apparatus for reducing latencies associated with interrupt/exception handling, and allowing increased flexibility in the provision of interrupt service routines.
2. Description of the Related Art
A conventional computer system 10 is shown in FIG. 1, and includes one or more central processing units (CPUs) 12a, 12b and 12c, a main memory unit 14 (such as random access memory or RAM) that is used by the processing units to carry out program instructions. Computer system 10 also includes one or more input/output (I/O) units 16a, 16b, and 16c, such as a display monitor, keyboard, pointing device (mouse), and a permanent memory device (such as a hard disk or floppy diskette) for storing the computer""s operating system and user programs. Computer system 10 may have many additional components which are not shown, such as serial, parallel and universal bus ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter might be used with a video display monitor, or a memory controller might be used with memory 14. Also, processing units 12a, 12b and 12c may each be comprised of several components, such as the processor core (which includes various registers and logic units), one or more memory caches, and a bus interface.
In earlier computer systems, the processing unit(s) communicated with the other devices by a single system bus 18, but later computer systems eased loading of the system bus by providing a second, I/O bus 17 which is connected to the various I/O devices 16a, 16b, and 16c and to system bus 18 by a bus bridge 19. I/O bus 17 may be any suitable bus useful for interconnecting the various I/O devices mentioned above as well as other devices such as a local area network (LAN) adapter. Exemplary bus standards include the ISA (industry standard architecture) bus, the EISA (extended industry standard architecture) bus, and the PCI (peripheral component interconnect) bus. Other means can also be provided for the various system devices to communicate with each other, such as direct memory access (DMA) channels which allow devices to communicate directly with one another, i.e., bypassing the processing units.
During I/O operations, various I/O devices (or the software device drivers controlling them) may issue xe2x80x9cinterruptxe2x80x9d signals to cause a processing unit to suspend its current procedure and save its status, and temporarily transfer control to a special routine such as an interrupt handler which then carries out a particular set of predetermined instructions to attend to the cause of the interrupt. Interrupts can occur during normal device operation, or due to abnormal (Unexpected) circumstances, i.e., an xe2x80x9cexception.xe2x80x9d A processor can further receive multiple interrupts from different sources in which case a set of interrupt priorities is used to determine which signal is handled first. After handling of the interrupt signal, control returns to the procedure that was being executed by the processing unit.
Many advances have allowed computer systems to operate at higher speeds, such as by increasing cache size and complexity. It is not always possible, however, to take full advantage of these speed gains due to other problems, such as the frequency of I/O operations. Two components of I/O operations that slow a system down are the interrupt processing delays (latencies) and the relatively slow operation of the I/O busses. Also, new adapter cards are placing shorter interrupt latency requirements on systems, due to faster communications line speeds and faster devices. Again, this problem is multiplied in a tiered-bus structure.
To address the latency problems associated with I/O operations, some computer systems add special hardware for dealing with interrupt handling outside of the main processing unit(s). For example, the AS/400 computing system marketed by International Business Machines Corp. (IBM, assignee of the present invention) employs an I/O processor (IOP) to move the interrupt processing closer to the I/O devices. A similar design, described in U.S. Pat. No. 5,548,730, uses an intelligent bridge that contains a full microprocessor and its supporting functions (memory control, bus control). It requires both non-volatile and volatile memory attached to boot the processor and run the functional code, and is thus a relatively expensive approach.
Another design is disclosed in U.S. Pat. No. 5,555,430, in which interrupts in a symmetric multi-processing (SMP) system are routed to a central interrupt control unit which interfaces directly with the processing units and the I/O devices. This approach does not fully address interrupt latency issues since it only allows the system to route the interrupt to a processor running the lowest priority task.
In the IBM PowerPC architecture, interrupt service routines (ISRS) are mapped to fixed memory locations. Usually the addresses are mapped from 0x00000100 through 0x00002000 (or through 0x00003000). The only means of relocating the interrupts, e.g., for a IBM PowerPC 600 series (60x) processor, is through the IP bit in the machine state register (MSR) which moves the block of interrupts to 0xFFF00100 through 0xFFF03000 (or to 0XFFFFFFFF FFF00100 through 0XFFFFFFFF FFF03000). The IBM 40x processor also introduced the concept of critical interrupts, i.e., a set of interrupts defined by the architecture to have a higher priority than the other non-critical interrupts. In a truly embedded environment, both the relatively fixed interrupt locations and the fixed definition of which interrupts are critical and non-critical are very limiting.
Both the 60x and 40x interrupt vector methods require 4KB to 12KB of contiguous memory reserved for ISR usage. Furthermore, the interrupts are spaced on 256-byte boundaries, so each ISR must be handled in 64 instructions or branch to other memory. For some interrupts, such as the ones that simultaneously handle illegal instructions, privilege violations, and program traps, 256 bytes is far too little space. In an embedded application, some interrupts are more time-critical than others. Having these service routines stored in memory embedded within the chip can greatly improve performance. Having error recovery routines in on-chip memory can allow the processor to recover from off-chip bus or memory errors. The 40x method of a predefined definition of which interrupts are considered critical does not allow the user the flexibility to tune the processor to the user""s application.
Yet another design for handling interrupts in an improved manner is shown in U.S. Pat. No. 5,473,763. According to that method, interrupt vectors are loaded directly into an address register to minimize overhead of processing interrupts. The address registers are located in xe2x80x9cstreamlined signal processorsxe2x80x9d which are part of the main processor complex. Provision of such a data storage processor is relatively expensive, as with the above-noted approach. Also, providing a processor as part of the main CPU complex is more limiting, since it cannot be scaled for multi-bus systems, and still has the problems attributed to the I/O latency issues. Designs such as that disclosed in U.S. Pat. No. 5,557,764 require xe2x80x9cinjectingxe2x80x9d interrupts from on-chip RAM, but still do not allow an ISR to selectably reside either on- or off-chip.
In light of the foregoing, it would be desirable to devise a method of dynamically locating ISR""s in one or more designated memory spaces, so as to reduce overall interrupt service latency. It would be further advantageous if a user could categorize interrupts as critical or non-critical in any manner found to be beneficial.
It is therefore one object of the present invention to provide an improved method of handling interrupts (including exceptions) in a computer system.
It is another object of the present invention to provide such a method which advantageously placed interrupt service routines on-chip or off-chip as necessary.
It is yet another object of the present invention to provide such a method that further allows a user to define which interrupts are to be considered critical.
The foregoing objects are achieved in a method of handling an interrupt request in a computer system, generally comprising the steps of programmably setting an override address associated with a specific interrupt service routine, receiving an interrupt request corresponding to the interrupt service routine, and servicing the interrupt request using the interrupt service routine based on the override address. The override address is different from a power-on default address associated with the same interrupt service routine. The method may further involve a determination of whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Where multiple ISRs are so stored, the limitation of prior art ISR boundaries may be overcome by spacing the override addresses apart by more than 256 bytes. The override address may point to a branch instruction for the interrupt service request. In the preferred embodiment, override address registers are accessed via the special purpose registers of the processing unit. In particular, a validation bit may be turned on in response to the setting of the override address, and both the default address and the override address are provided as separate inputs to a multiplexing device which is controlled by the validation bit. The override address is accordingly forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus noncritical interrupts.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.